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LabVIEW Simnuation Interface Toolkit 3.0.1 Win32Eng LabVIEW8.0仿真接口工具包SIT3.0.1下载

3.0.1~LV8
文件大小: 56994304 字节 (54.35 MB)
修改日期: 2010-04-25 04:21
MD5: d48e969479b57889f945ce08081ea1d1（重复一致，可秒传）
SHA1: f2865106c4991fc914c344662115a3d8a873b403
SHA256: cbf73f17b85ec3c5a0561dfece14b7a8df7fe2368a7cc9adc0ad3e87d8e6af9f
CRC32: c225b694

百度网盘和NI官方下载地址：

LabVIEW Simnuation Interface Toolkit 3.0.1 Win32Eng LabVIEW8.0仿真接口工具包SIT3.0.1下载

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(出处: 视觉论坛VISIONBBS|视觉之家VISIONHOME)

LabVIEW Simulation Interface Toolkit 3.0.1 Readme

• When converting a model to a model DLL, you can improve conversion time by excluding signals from virtual blocks. However, if you exclude these signals, you cannot probe these signals unless you add a non-virtual block to the signal. Complete the following steps to exclude signals from virtual blocks.
  

• Launch the Simulink application software and load the model you want to convert.

• For the MathWorks, Inc. MATLAB® application software release 13, select Simulation»Simulation parameters to launch the Simulation Parameters dialog box.
  
  For the MathWorks, Inc. MATLAB® application software release 14, select Simulation»Configuration Parameters to launch the Configuration Parameters dialog box.

• Click the Real-Time Workshop tab.

• Click the Browse button to launch the System Target File Browser dialog box.

• Select nidll.tlc—NI Real-Time Target from the list.

• Click the OK button.

• For the MathWorks, Inc. MATLAB® application software release 13, enter nidll.tlc -aNiDisableVirtualBlockMap=1 in the System target file text box.
  
  For the MathWorks, Inc. MATLAB® application software release 14, enter -aNiDisableVirtualBlockMap=1 in the TLC options text box.
  

• If you are using SIT 3.0.1 with LabVIEW 7.1.1fx, you cannot view custom FPGA VIs. Workaround: After you click the Browse button in the Add FPGA Device dialog box, select View All from the File Type drop-down list. If you are using a pre-defined FPGA VI that ships with SIT 3.0.1, you must rename the VI on disk to sitfpga <device> 7_1_1_fx devicetype.vi, where <device> is the FPGA device, x is the LabVIEW update number, and devicetype is master or slave.

• If you are running a simulation on the NI PXI-8146, you must install the LabVIEW Real-Time Module to the NI PXI-8146 before installing the Simulation Interface Toolkit 3.0.1.

• If you open a host VI you saved in SIT 3.0, the SIT Connection Manager dialog box loads slowly the first time you launch this dialog box. The load time reduces the next time you launch this dialog box.

• If you create a mapping using the SIT Connection Manager dialog box and then click the Cancel button, the new mapping is retained.

• SIT 3.0.1 includes two VIs that enable datalogging for a custom host VI. These VIs, SIT FinishLogging VI and SIT Log Continuously VI, are located in the labviewi.libddonsSimulation Interfacedriverblocks directory.

• If you use the Project Explorer window to deploy a driver VI to a real-time target, you must run that VI before the host VI can connect to it. You must complete the following steps before running the driver VI.
  
  
  If you build the model DLL again after running the simulation, you must remove the driver VI from memory before running simulation again.
  
  If you use the SIT Connection Manager dialog box to create and deploy a driver VI, you do not need to use the Project Explorer window.

• Right-click the real-time (RT) target in the Project Explorer window and select Properties from the shortcut menu.

• Select VI Server: Configuration in the Category list.

• Place a checkmark in the TCP/IP checkbox.

• Select VI Server: Machine Access in the Category list.

• Click the Add button, and enter the IP address of the host computer in the Machine name/address text box.

• Select VI Server: Exported VIs in the Category list.

• Click the Add button, and enter the path and name of the driver VI in the Exported VI text box.

• Click the OK button.
  

• If you run a driver VI on a non-RT target and want to connect to the driver VI by using a networked PC, you must run the driver VI before attempting to connect to it from the networked PC. You also must complete the following steps on the PC running the driver VI.
  

• Launch LabVIEW and open the driver VI.

• Select Tools»Options from the pull-down menu.

• Select VI Server: Configuration in the Category list.

• Place a checkmark in the TCP/IP checkbox.

• Select VI Server: Machine Access in the Category list.

• Click the Add button, and enter the IP address of the networked PC in the Machine name/address text box.

• Select VI Server: Exported VIs in the Category list.

• Click the Add button, and enter the path and name of the driver VI in the Exported VI text box.

• Click the OK button.
  

• If you are running a multirate simulation using an NI FPGA device and a lower-priority task finishes late, this late finish forces the driver VI to report an overrun, which halts the simulation. This behavior occurs regardless of whether the Halt Simulation on Any Task Overrun checkbox contains a checkmark.
  

Accessing the Help

LabVIEW Simulation Interface Toolkit 3.0 Readme

System Requirements

• The MathWorks, Inc. MATLAB® / Simulink® application software release 13.x or 14.0, 14.1, 14.2, 14.3
  

• The MathWorks, Inc. Real-Time Workshop® release 13.x or 14.0. 14.1, 14.2, 14.3

• Microsoft Visual C++ 6.0. You can use Microsoft Visual C++ .NET 2003 only if you installed the LabVIEW 7.1.1 maintenance release.
  

• National Instruments LabVIEW Real-Time Module 7.1.x for ETS Targets.

• (Optional) National Instruments LabVIEW FPGA Module 1.1.x, for customized FPGA VIs used in real-time simulations involving FPGA devices
  

What's New in 3.0

• Improved Model Parsing Performance—Models developed in the Simulink simulation environment load much faster in SIT 3.0 than in SIT 2.0.x.

• Configurable Driver VIs for National Instruments FPGA Devices and CAN Interfaces—Use the SIT Connection Manager dialog box to create mappings between a model DLL and NI FPGA devices and CAN interfaces.

• Editing Multiple Parameters at Run Time—Use the Edit Multiple Parameters dialog box to change the value of multiple parameters at once while the simulation is running.

• Modifying Mappings at Run Time—Use the Remap Controls and Indicators dialog box to modify mappings between the host VI and the model while the simulation is running.

• Dynamic Connection Manager—The SIT Connection Manager dialog box now detects controls and indicators you place on the front panel of the host VI at edit time.

• Single SignalProbe Block—Use a single block to probe all model signals.

• Datalogging—Use the Datalogging Settings dialog box to log simulation data to a file you specify.

• Global Signal Decimation—You can apply a global decimation factor to signals the execution host returns.

• Multi-rate Simulations—SIT 3.0 supports preemptive multi-rate execution on NI FPGA devices and CAN interfaces.
  

Support for Real-Time Targets

• PXI/PCI
  

• NI PXI-8145

• NI PXI-8146

• NI PXI-8156B

• NI PXI-8170

• NI PXI-8175

• NI PXI-8176

• NI PXI-8184

• NI PXI-8186

• NI PXI-8187

• NI PXI-8196

• NI PCI-7041. Refer to the Known Issues section of this document for information about using the PCI-7041 in a real-time simulation.
  

• FieldPoint
  

• NI FP-2010

• NI FP-2015

• NI cFP-2010

• NI cFP-2020
  

• CompactRIO
  
  

• NI cRIO-9961
  

• NI PCI-7811R

• NI PXI-7811R

• NI PCI-7813R

• NI PXI-7813R

• NI PCI-7831R

• NI PXI-7831R

• NI PCI-7833R

• NI PXI-7833R

• NI cRIO-9103
  

Accessing the Help and Examples

Upgrading from SIT 2.0.x

• If you load a host VI saved in SIT 2.0.x and launch the SIT Connection Manager dialog box, SIT 3.0 prompts you to convert the host VI from 2.0.x format to 3.0 format. The conversion process preserves control/indicator mappings and all block diagram code SIT 2.0.x did not generate. The conversion process does not preserve any edits you made to the block diagram code SIT 2.0.x generated. If the path to the model is invalid, SIT 3.0 prompts you to specify a valid path.

• SIT 3.0 does not convert driver VIs that SIT 2.0.x generated. You must rebuild driver VIs for use in real-time simulations.

• The Simulation Interface Toolkit 3.0 deprecates the following VIs: SIT Start Server, SIT Step Model, SIT Stop Server, SIT Wait for Run Command, SIT Finalize Model (No Server), SIT Initialize Model (No Server), SIT Map Model Parameters, SIT Set Model Parameters (No Server), SIT Get Error, SIT Register, SIT Unregister, and SIT Write to RT.

• The Simulation Interface Toolkit 3.0 relies heavily upon the SIT Connection Manager dialog box. National Instruments recommends you use this dialog box to create host VIs and driver VIs.
  

Installation/Upgrading Instructions

• Insert the LabVIEW Simulation Interface Toolkit 3.0 CD.

• Run the setup.exe program.

• Follow the instructions that appear on the screen.
  

Development Tips

• If you installed the LabVIEW 7.1.1 maintenance release, you must mass compile the following:
  

• labviewprojectsitwiz.llb

• The labviewi.libddonsSimulation Interface directory
  

• By default, DAQmx scripted code assumes measurements are differential. To change to reference single-ended (RSE) measurements, find the DAQmx Create Virtual Channel VI, which is called as a subVI from the driver VI, and select RSE for the input terminal configuration control.

• Driver VIs running on FPGA devices use the hardware settings for channel measurements.

• For all supported NI FPGA devices, driver VIs assume pulse-width modulation (PWM) input channels have a period greater than 1 KHz. Workaround: Change the default values of the _timeout controls of the FPGA VI and recompile the FPGA VI. The new value is (40 MHz / w), where w is the actual frequency of the PWM input channel. The FPGA VIs are located in the labviewi.libddonsSimulation Interface_IOTypesNI FPGAFPGA IO VIsdirectory.

• For real-time simulations using LabVIEW 7.1.1, complete the following steps to improve Ethernet performance on a closed/private network using crossover cables.
  

• Launch National Instruments Measurement & Automation Explorer (MAX).

• Expand the Remote Systems category.

• Select the RT Target.

• Select Advanced Ethernet Settings.

• Set Duplex to Half.
  

• Open an FTP connection to the RT target and download the c: i-rt.ini file to the host.

• Edit the ni-rt.ini file and add SendBufferSize = 65535 under the [lvrt] section. This number equates to a 64KB buffer size. You may experiment using other buffer sizes with a minimum of 1024 and a maximum of 65535.

• Upload the edited ni-rt.ini file back to the RT target and reboot the controller.

• Built-in Ethernet Port: If using the built in ethernet port of a PXI or CVS real-time controller, then you must set the controller to use half-duplex mode for communication.
  If you are using LabVIEW 7.1, you only can set the controller to use half-duplex mode for communication.
  

• To create a driver VI using PCI FPGA devices inside the host computer, you manually must execute NIVisaServer.exe. To execute this program, launch MAX, right-click the NIVisaServer.exe item from the My System»Software»NI-VISA tree, and select Launch NIVisaServer.exe from the shortcut menu. After you execute this program, PCI FPGA devices appear in the Configure FPGA Devices dialog box when you create a driver VI.
  

Known Issues

• If you are using the MATLAB® application software release 13.0, SIT 3.0 might not install the necessary support files. Workaround: Run the SIT 3.0 installer again, choose to install MATLAB Support and the MATLAB application software release 13 support, and specify the path on your hard drive to the MATLAB application software release 13.

• If you installed the MATLAB application software files as read-only, the SIT Server does not start automatically and you cannot place a SignalProbe block in the Simulink window. You must modify the startup.m file in order to make these changes. Refer to the Communicating with the SIT Server topic in the Simulation Interface Toolkit Help for information about making these changes.
  

• If you select custom signals to log in the Datalogging Settings dialog box and then close the dialog box, the signals tree does not automatically highlight the signals you selected. This same issue occurs if you map more than one model signal to a host VI indicator.

• You cannot build an executable from the host VI.

• The target model of a model reference block cannot contain a SignalProbe block. Placing a SignalProbe block in a target model prevents the simulation from running.

• If you do not specify any signals to probe, SIT 3.0 does not return the current simulation time in the Simulation Details dialog box.

• SIT 3.0 returns error –14103 if you use non-English regional settings or if you use a comma as the decimal separator when specifying a double-precision number. Workaround: Launch the Windows Control Panel and double-click the Regional and Language Options icon. On the Regional Options page, select English (United States) from the pull-down list in the Standards and formats section.

• Waveform charts might scroll incorrectly to a slightly different time than the end time of the simulation. For example, the chart might display 299.90 instead of 300.00. This is an issue with the LabVIEW chart. Workaround: Enter the correct end time into the scale of the chart to show the appropriate data.

• Using more than one XY graph on the front panel of the host VI causes unexpected results.

• If you run a simulation more than once, an XY graph does not clear between runs.

• LabVIEW 7.1.x contains a known issue that affects host VIs. If you minimize a host VI window that contains a chart, the chart might display erroneous lines after you restore the host VI window.
  

• The sub VIs of the driver VI are reentrant. If you directly are running a driver VI while LabVIEW is targeted to RT, you must abort the driver VI to stop the driver VI. The stop button for the driver VI is on the base rate loop subVI. However, because that VI is reentrant, you cannot press the stop button. Workaround:Make the base rate loop subVI non-reentrant for debugging purposes.

• SIT 3.0 cannot probe signals from top-level model inputs with spaces in the names.

• If you create mappings between a model DLL and only AI or only AO channels on a DAQ device, the driver VI returns error –200429.

• The NI PCI-7041 does not have a separate IP address. To connect a host VI with the SIT Server running on a NI PCI-7041, you must start the driver VI on the NI PCI-7041 using either of the methods described in the Building a Driver VI Startup Application or Downloading the Driver VI using the LabVIEW Real-Time Module topics of the Simulation Interface Toolkit Help. Using the RT Proxy Watcher utility, you must determine the port to which the NI PCI-7041 virtual FTP port is mapped on the host computer. Refer to the NI Developer Zone, located at ni.com/zone, for information about the RT Proxy Watcher. Enter Obtaining LabVIEW Real-time Proxy Port Mappings in the Search field to search for information about the RT Proxy Watcher.

• If you are using the NI cRIO-9103 FPGA device and you have only one customized FPGA VI in the appropriate directory, you cannot select that FPGA VI from the Add FPGA Device dialog box. Workaround: Copy the shipping cRIO-9103 FPGA VI out of the directory, and copy the custom FPGA VI into that directory.